1. Field of the Invention
The present invention relates to a read/write memory device with an embedded read-only pattern and also relates to a method for providing the same. This embedded read-only pattern will be shown to be particularly useful in a memory array device with an embedded self-test pattern
2. Background Art
Numerous memory array devices are well known in the art including static and dynamic memories of the read/write type. The present invention will be described in connection with a static read/write memory; however, it should be noted that the present invention is by no means limited to use with memory array devices of this type.
FIG. 1 shows a prior art 6-transistor static memory cell 10 having a symmetrical configuration of six transistors consisting of T.sub.1, T.sub.2 and T.sub.3 on the one hand, and T.sub.4,T.sub.5 and T.sub.6 on the other. In the description of the preferred embodiment, these transistors will be described as FET transistors, each of which has a source, gate and drain terminal. A voltage V.sub.dd is applied to the source and gate terminals of the transistors T.sub.2 and T.sub.4 whose drain terminals are connected to nodes 50 and 60, respectively. Also connected to nodes 50 and 60 are the source and gate terminals of the cross-coupled transistors T.sub.3 and T.sub.5 whose drain terminals are connected to ground through node 70. Also connected to nodes 50 and 60 are the drain terminals of transistors T.sub.1 and T.sub.6, respectively, whose gate terminals are connected to the word lines 30 of the memory cell 10. Finally, the source terminals of transistors T.sub.1 and T.sub.6 are connected to the bit lines 20 of the memory cell 10.
During memory operation, the cross-coupled configuration of T.sub.3 and T.sub.5 functions as a bistable latch, the state of which can be set or read using the bit lines 20 and word lines 30. To perform a write operation, a voltage imbalance is impressed across the nodes 50 and 60 so that the cross-coupled transistors T.sub.3 and T.sub.5 will be set to one of two bistable states, whereby a voltage representing a logical 1 or 0 will be maintained at the node 50, while a voltage representing an opposite logical value will be maintained at the node 60.
FIG. 2 is a simplified diagram of a memory array constructed of cells 10 of the type shown in FIG. 1. Only an exemplary section of a memory array is shown, i.e., a practical memory array would typically have a tremendous number of memory sells arranged along many more rows and many more columns. An example of a row in the illustrated memory array section is a first row consisting of memory cells A.sub.11, A.sub.12, A.sub.13, . . . Likewise, an example of a column in the memory array section is a first column consisting of the memory cells A.sub.11, A.sub.12, . . . Bit lines and word lines, which are not of importance in the description of the present invention, have been omitted. As can be seen in FIG. 2, the terminals 40 of the memory cells have been connected to lines 110 which, in turn, are connectable to a single voltage supply indicated by V.sub.dd.
Although the memory array devices described with reference to FIGS. 1 and 2 are of tremendous use in the world today, there remains the problem of testing to determine whether a memory array is properly functioning. In this regard, numerous testing approaches have been proposed. For example:
In U.S. Pat. No. 4,481,627, issued to Beauchesne et al, the testing of memory arrays within electronic assemblies is performed by using circuitry which can display a high impedance while the memory array is accessed and directly tested.
In U.S. Pat. No. 3,961,254, issued to Cavaliere et al, the input and output circuitry of a RAM is bypassed so that the embedded memory array can be accessed and directly tested.
U.S. Pat. Nos. 4,332,028, issued to Joccotton et al, and 3,805,152, issued to Ebersman et al, both disclose methods for measuring the AC parameters of a memory array by using an external recirculation technique.
Finally, U.S. Pat. No. 3,961,252, issued to Eichelberger, allows testing by converting circuitry, which is associated with an embedded memory array, to counters the outputs of which can be compared with the outputs from the memory array.
In the above-mentioned testing approaches and with prior art testing approaches in general, a binary test pattern must be loaded into the memory from the external world and, then unloaded from the memory to test for the proper operation of the memory. This procedure is disadvantageous because a binary test pattern must be stored and generated by an external device, and because the loading of the binary test pattern into the memory device increases the total testing time. Consequently, there exists a need for an improved approach whereby the need for external generation, and then loading, of the binary test pattern are eliminated. More specifically, there exists a need for a memory device which can store an embedded binary pattern which can be used as a self-test binary pattern.